1. Field of the Invention
The present invention relates to a semiconductor device, and in particular relates to a PIN diode device and the method for forming thereof.
2. Description of the Related Art
High power semiconductor devices are applied to integrated circuits with high voltage and high power. Traditional high power semiconductor devices are mainly used for devices with at least 18 volts or higher. The advantages of high power device technology include cost effectiveness and process compatibility. High power device technology has been widely used in display driver IC devices, power supply devices, power management fields, communications fields, autotronics fields, and industrial control fields, etc.
Traditional high power devices are provided with vertical double diffused MOSFETs (VDMOSFETs) and lateral double diffused MOSFETs (LDMOSFETs), wherein a double diffused MOSFET is a representative lateral structure and a trench power transistor is a representative vertical structure.
U.S. Pat. No. 6,194,761 discloses an N-type channel vertical double diffused MOSFET, wherein a vertical current is controlled by a junction field effect transistor effect resulting from the boundary of depletion regions of two P-type doped body regions and an epitaxial layer expending to a central region.
FIG. 1 shows a cross-sectional view of a traditional pseudo-VDMOS transistor device. As FIG. 1 shown, the high power pseudo-VDMOS transistor device comprises a P-type doped semiconductor substrate 11 and an N-type doped epitaxial layer 13 formed on the P-type doped semiconductor substrate 11. An N-type heavily doped buried region 23 is deposited between the P-type doped semiconductor substrate 11 and N-type doped epitaxial layer 13. Two P-type doped body regions 31, 37 are formed in the N-type doped epitaxial layer 13, respectively, and isolated from each other with a channel. A heavily doped drain region 21 is formed in the N-type doped epitaxial layer and isolated from the P-type doped body region 37 with an isolation region 15. An N-type deep heavily doped region 25 is extended from the heavily doped drain region 21 to the N-type heavily doped buried region 23. A pair of inversed type heavily doped source regions 33A, 33B are formed in the P-type doped body regions 31, 37, respectively, and a gate electrode 39 is disposed overlying the channel with a gate dielectric interposed therebetween. The high power semiconductor device is isolated from the other devices with a pair of P-type heavily doped regions 17 and a pair of P-type deep heavily doped regions 19. During operation of the device, the heavily doped drain region 21 is coupled to a drain voltage (VDD), and the heavily doped source regions 33A, 33B and gate electrode 39 are coupled to a source voltage (VSS). The current path is represented by a boldfaced dotted line. The advantage of the pseudo-VDMOS transistor power device 10 is its high compatibility with other CMOS devices. However, the device region isolated by the P-type deep heavily doped regions 19 occupies too much area, which makes device integration difficult.
U.S. Pat. No. 6,531,355 discloses a lateral double diffused MOS (LDMOS) transistor device. The operating principle of a traditional LDMOSFET is the same as any other MOSFET. All MOSFET's control current flowing between the drain and the source by a channel resulting from the gate voltage.
FIG. 2 shows a cross-sectional view of a traditional LDMOS transistor device. As FIG. 2 shown, a high power LDMOS transistor device 50 comprises a P-type doped semiconductor substrate 51 and an N-type doped epitaxial layer 53 formed on the P-type doped semiconductor substrate 51. A P-type doped body region 67 is formed in the N-type doped epitaxial layer 53. An N-type deep heavily doped region 65 is formed in the N-type doped epitaxial layer 53. An N-type heavily doped drain region 61 is formed in the N-type deep heavily doped region 65 and isolated from the P-type doped body region 67 with an isolation region 55 and a channel. A pair of inversed type heavily doped source regions 63A, 63B are formed in the P-type doped body region 67 and a gate electrode 69 is disposed overlying the channel with a gate dielectric interposed therebetween. The high power semiconductor device is isolated from the other devices with a pair of P-type heavily doped regions 57 and a pair of P-type deep heavily doped regions 59. During operation of the device, the heavily doped drain region 61 is coupled to a drain voltage (VDD), the heavily doped source regions 63A, 63B are coupled to a source voltage (VSS), and gate electrode 69 is coupled to gate voltage (VG). The current path is represented by a boldfaced dotted line. The advantageous of the LDMOS transistor power device 50 include ease of production and high compatibility with CMOS semiconductor technology processes. However, LDMOSFET's raise voltage tolerances by increasing the length of the drift region near the drain, which in turn consumes a lot of area. Moreover, surface field of a double diffused transistor also limits the voltage tolerance of transistor.
Therefore, a high power semiconductor power device with the high voltage tolerance feature of VDMOS and LDMOS transistor devices and smaller volume is needed.